Automatic Abstraction for Verification of Timed Circuits and Systems

Hao Zheng, Eric Mercer, Chris Myers

To appear at 13th Conference on Computer-Aided Verification (CAV01), Paris, France, 18-22 July 2001


Abstract

This paper presents a new approach for verification of asynchronous circuits by using automatic abstraction. It attacks the state explosion problem by avoiding the generation of a flat state space for the whole design. Instead, it breaks the design into sub-blocks and conducts verification on each of them. Using this approach, the speed of verification improves dramatically.


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